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MITSUBISHI SEMICONDUCTOR MITSUBISHI SEMICONDUCTOR
PS11034 PS11034
FLAT-BASE TYPE FLAT-BASE TYPE INSULATED TYPE INSULATED TYPE
PS11034
INTEGRATED FUNCTIONS AND FEATURES
* Converter bridge for 3 phase AC-to-DC power conversion. * 3 phase IGBT inverter bridge configured by the latest 3rd. generation IGBT and diode technology. * Inverter output current capability IO (Note 1): Type Name Motor Rating IO (100%) IO (150%; 60sec) 7.5Arms PS11034 0.75 kW/200V AC 5.0Arms (Note 1) : The inverter output current is assumed to be sinusoidal and the peak current value of each of the above loading cases is defined as : IOP = IO x 2, TC < 100C
INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS:
* P-Side IGBTs : Drive circuit, high-level-shift circuit, bootstrap circuit supply scheme for Single Control-Power-Source drive, and under voltage (UV) protection. * N-Side IGBTs : Drive circuit, DC-Link current sense and amplifier circuits for overcurrent protection, control-supply under-voltage protection (UV), and fault output (FO) signaling circuit. * Fault Output : N-side IGBT short circuit (SC), over-current (OC), and control supply under-voltage (UV). * Inverter Analog Current Sense : N-Side IGBT DC-Link Current Sense. * Input Interface : 5V CMOS/TTL compatible, Schmitt Trigger input, and Arm-Shoot-Through interlock protective function.
APPLICATION Acoustic noise-less 0.75kW/200V AC Class 3 phase inverters, motor control applications, and motors with built-in small size inverter package
PACKAGE OUTLINES
741 60 36
0.4
16.50.5 Terminals Assignment : 1. CBU+ 2. CBU- 3. CBV+ 4. CBV- 5. CBW+ 6. CBW- 7. VD 8. UP 9. VP 10. WP 11. UN 12. VN 13. WN 14. FO 15. Vamp 16. GND 21. P1 22. R 23. S 24. T 25. N1 26. P2 27. U 28. V 29. W 30. N2
4
12
34
56
7 8 9 10 12 14 16 11 13 15
4
631
2-R
2.2
50.70.8
5
4.5
(25.7)
2
0.6
30.5
25
15
2-R
1.2 5.08
21 22 23 24 25 26 27 28 29 30
250.5
4.5
4
40 0.6
9
45.72 (69) 2
3.5
4-R3 8.50.5
55.5
2
16.50.5
Type name,LotNo.
(Fig. 1)
Jan. 2000
MITSUBISHI SEMICONDUCTOR
PS11034
FLAT-BASE TYPE INSULATED TYPE
INTERNAL FUNCTIONS BLOCK DIAGRAM
P1 R S T N1 UV Protection P2
Input signal conditioning (Interlock circuit)
VD UP VP WP UN VN WN FO V(amp)
Level shifter
Drive circuit
U V W
OC/SC Protection
+-
UV Protection
Drive circuit
Fo Circuit
GND
N2
(Fig. 2)
MAXIMUM RATINGS (Tj = 25C) INVERTER PART
Symbol VCC Item Supply voltage Condition Applied between P2-N2 Ratings 450 500 600 600 15 (30) Unit V V V V A
VCC(surge) Supply voltage (surge) Applied between P2-N2, Surge-value VP or VN Each output IGBT collector-emitter static voltage Applied between P2-U.V.W, U.V.W-N2 VP(S) or VN(S) Ic(Icp) Each output IGBT collector-emitter switching voltage Each output IGBT collector current Applied between P2-U.V.W, U.V.W-N2 TC = 25C, "( )" means IC peak value
CONVERTER PART
Symbol VRRM Ea IO IFSM I2t Item Repetitive peak reverse voltage Recommended AC input voltage DC output current Surge (non-repetitive) forward current I2t for fusing 3 rectifying circuit 1 cycle at 60Hz, peak value non-repetitive Value for one cycle of surge current Condition Ratings 800 220 15 150 93 Unit V Vrms A A A 2s
CONTROL PART
Symbol VD, VDB VCIN VFO IFO Iamp Supply voltage Input signal voltage Fault output supply voltage Fault output current DC-Link IGBT current signal Amp output current Item Ratings -0.5 ~ 20 -0.5 ~ +7.5 -0.5 ~ +7.5 15 1 Unit V V V mA mA
Jan. 2000
MITSUBISHI SEMICONDUCTOR
PS11034
FLAT-BASE TYPE INSULATED TYPE
TOTAL SYSTEM
Symbol Tj Tstg TC VISO -- Item Junction temperature Storage temperature Module case operating temperature Isolation voltage Mounting torque Condition (Note 2) -- (Fig. 3) 60 Hz sinusoidal AC applied between all terminals and the base plate for 1 minute. Mounting screw: M4 Ratings -20 ~ +125 -40 ~ +125 -20 ~ +100 2500 0.98 ~ 1.47 Unit C C C Vrms N*m
(Note 2) : The indicated values are specified considering the safe operation of all the parts within the ASIPM. The max. ratings for the ASIPM power chips (IGBT & FWDi) is Tj < 150.
CASE TEMPERATURE MEASUREMENT POINT
TC
(Fig. 3)
THERMAL RESISTANCE
Symbol Rth(jc)Q Rth(jc)F Rth(jc)FR Rth(cf) Junction to case Thermal Resistance Contact Thermal Resistance Item Inverter IGBT (1/6) Inverter FWDi (1/6) Converter Di (1/6) Case to fin thermal, grease applied (1 Module) Condition Ratings Min. -- -- -- -- Typ. -- -- -- -- Max. 2.8 3.9 4.8 0.074 Unit C/W C/W C/W C/W
ELECTRICAL CHARACTERISTICS (Tj = 25C, VD = 15V, VDB = 15V unless otherwise noted)
Symbol VCE(sat) VEC VFR IRRM ton tc(on) toff tc(off) trr FWDi reverse recovery time Item Collector-emitter saturation voltage FWDi forward voltage Condition Tj = 25C, Input = ON, Ic = 15A, VD = VDB = 15V (Shunt voltage drop not included) Tj = 25C, -IC = 15A Ratings Min. -- -- -- -- 0.3 -- -- -- -- Typ. -- -- -- -- 0.6 0.5 1.6 0.5 0.12 Max. 2.9 2.9 1.5 8 1.5 1.0 2.5 1.3 -- Unit V V V mA s s s s s
Tj = 25C, IFR = 10A Converter diode voltage Converter diode reverse current VR = VRRM, Tj = 125C 1/2 Bridge inductive, Input = 5V 0V VCC = 300V, IC = 15A, Tj = 125C VD = 15V, VDB = 15V Note: ton, toff include delay time of the internal control circuit.
Switching times
Short circuit endurance @VCC 400V, Input = 5V 0V (One-Shot) (Output, Arm, and Load Short Circuit Modes) -20C Tj (start) 125C, 13.5V VD = VDB 16.5V Switching SOA @VCC 400V, Input = 5V 0V, Tj 125C IC < OC trip level, 13.5V VD = VDB 16.5V
* No destruction * FO output by protection operation * No destruction * No protecting operation * No FO output
Jan. 2000
MITSUBISHI SEMICONDUCTOR
PS11034
FLAT-BASE TYPE INSULATED TYPE
ELECTRICAL CHARACTERISTICS (Tj = 25C, VD = 15V, VDB = 15V unless otherwise noted)
Symbol ID IDB Vth(on) Vth(off) Ri fPWM tdead tint Vamp(100%) Vamp(200%) Vamp(250%) Vamp(0) OC tOC SC tSC UVD UVDr UVDB UVDBr tdV tFO IFo(H) IFo(L) Item Circuit current (Average) Circuit current (Average) Input on threshold voltage Input off threshold voltage Input pull-up resistor PWM input frequency Arm shoot-through blocking time Input interlock sensing Inverter DC-Link IGBT current sense voltage output signal Inverter DC-Link IGBT current sense voltage output limit Over current trip level Over current delay time Short circuit trip level Short circuit delay time Trip level Reset level Supply circuit under Trip level voltage protection Reset level Delay time Fault output pulse width Fault output current Condition Tj = 25C, VD = 15V, Vin = 5V Tj = 25C, VD = VDB = 15V, Vin = 5V Min. -- -- 0.8 2.5 -- 1 2.2 -- 1.5 3.0 5.0 -- 14.2 -- -- -- 11.0 11.5 10.1 10.6 -- 1.0 -- -- Ratings Typ. -- -- 1.4 3.0 50 -- -- 100 2.0 4.0 -- 50 17.7 10 30 2 12.0 12.5 10.8 11.3 10 1.8 -- -- Max. 50 5 2.0 4.0 -- 15 -- -- 2.5 5.0 -- 100 25.0 -- -- -- 13.0 13.5 11.6 12.1 -- -- 1 15 Unit mA mA V V k kHz s ns V V V mV A s A s V V V V s ms A mA
Applied between input terminal-inside power supply TC 100C, Tj 125C Relates to corresponding inputs (Note 3) TC = -20C ~ +100C Relates to corresponding input (Fig. 6) IC = IOP(100%) VD = 15V Tj = 25C (Fig. 4) IC = IOP(200%) VD = 15V IC = IOP(250%) (Fig. 4) IC = 0A Tj = 25C (Fig. 5) Tj = 25C (Fig. 5) Tj = 25C (Fig. 5) Tj = 25C (Fig. 5)
TC = Tj = 25C
(Fig. 5)
Tj = 25C Open collector output
(Note 4) (Note 4)
(Note 3) : The dead-time has to be set externally by the CPU; it is not part of the ASIPM internal functions. (Note 4) : Fault output signaling is given only when the internal OC, SC, & UV protection circuits are activated. The OC, SC and UV protection (and fault output) operate for the lower arms only. The OC and SC protection Fault output is given in a pulse format while that of UV protection is maintained throughout the duration of the under-voltage condition.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VD VDB VD, VDB VCIN(ON) VCIN(OFF) tdead TC fPWM tXX Item Supply voltage Supply voltage Supply voltage Supply voltage ripple Input on voltage Input off voltage Arm shoot-through blocking time Module case operating temperature PWM Input frequency Allowable minimum input on-pulse width Condition Applied across P2-N2 terminals Applied between VD-GND Applied between CBU+ & CBU-, CBV+ & CBV-, CBW+ & CBW- Applied between UP * VP * WP * UN * VN * WN and GND Relates to corresponding inputs TC 100C, Tj 125C Ratings Min. -- 13.5 13.5 -1 0 4.0 2.2 -- -- 1
Vamp
Typ. 300 15.0 15.0 -- -- -- -- -- -- --
Max. 400 16.5 16.5 +1 0.8 5.0 -- 100 15 --
Unit V V V V/s V V s C kHz s
5
INVERTER DC-LINK IGBT CURRENT ANALOGUE SIGNALING OUTPUT (TYPICAL)
4
VD = 15V Tj = 25C Vamp (200%)
Vamp (V)
3
2 Vamp (100%) 1
0 0
(Fig. 4)
200 300 100 Actual Load Peak Current (%), (IC = IO! 2)
Jan. 2000
MITSUBISHI SEMICONDUCTOR
PS11034
FLAT-BASE TYPE INSULATED TYPE
CURRENT ABNORMALITY PROTECTIVE FUNCTIONS
Ic(A) Short circuit trip level SC Over current trip level
OC
Collector current 0 2 10 tw (s)
Protection is achieved by monitoring and filtering the N-side DC-Bus current. The over-current protection is activated (after allowing a filtering time of 10 s) when the line current reaches 250% of the rated load-current IO (rms). Similarly, the short circuit protection is activated (after allowing a filtering time of 2 s) when the line current reaches twice the rated collector-current (IC). When a current trip-level is exceeded (OC or SC), all the N-side IGBTs are intercepted (turned OFF) and a fault-signal is output. After the fault-signal output duration (1.8 ms - typ.), the interception is Reset at the following OFF input signal. However, since the fault may be repetitive, it is recommended to stop the system after the fault-signal is received and check the fault. The trip-level settings described above are summarized in the following figure:
(Fig. 5)
ARM-SHOOT-THROUGH INTER-LOCK PROTECTIVE FUNCTION
P-Side Input Signal : VCIN(p) ON N-Side Input Signal : VCIN(n) ON a3 P-Side IGBT Gate : VGE(p) 0 a2 b3 0 a1 a4 b1 b4
b2
N-Side IGBT Gate : VGE(n)
(Fig. 6) Description: (1) During the ON-State of either of the upper-arm or the lower-arm IGBT, the inter-lock protection circuit blocks any erroneous ON pulses (resulting from input noise) from triggering the other arm IGBT and thus it prevents the arm-shoot-through situation. (2) When two ON-signals are received for both the upper and the lower arms, the signal received first will be passed to the IGBT and the second signal will be blocked. The second signal will be passed to its corresponding IGBT immediately after the first signal is OFF. Note: This protective function provides no fault signaling output. The Dead-Time has to be set using the micro-controller (CPU). Operation: a1. P-side normal ON-signal P-side IGBT gate turns ON. a2. N-side erroneous ON-signal N-side IGBT gate remains OFF. a3. While P-side ON-signal remains P-side IGBT gate remains ON. a4. N-side normal ON-signal N-side IGBT gate turns ON. N-side normal ON-signal N-side IGBT gate turns ON. Simultaneous ON-signals P-side IGBT gate remains OFF. N-side receives OFF-signal N-side IGBT gate turns OFF. Immediately after (b3) P-side IGBT gate turns ON.
b1. b2. b3. b4.
RECOMMENDED I/O INTERFACE CIRCUIT
5V
5V 5.1k R
VD(15V)
ASIPM
UP,VP,WP,UN,VN,WN Fo V(amp)
CPU
R 10k 0.1nF 0.1nF
(Fig. 7)
GND(Logic)
Jan. 2000

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